Design exploration and measurement benchmark of integrated-circuits based on graphene field-effect-transistors : towards wireless nanotransceivers

This doctoral thesis approaches the design requirements for future high / ultra-high data rate (from 100 Mbps to 100 Gbps) nanotransceivers (nanoTRx) applied to wireless nanonetworks which imply short/ultra-short distance ranges (3 cm ¿ 3 m). It explores graphene field-effect-transistors (GFET), by simulation against measurement benchmarks, as a potential solution for implementing large-signal high-frequency circuits, by virtue of graphene¿s one-atom thickness and high carrier-mobility extraordinary properties. Finally, the thesis discusses the challenges faced by GFETs, such as zero-bandgap and high metal-graphene contact-resistance, to be able to propose improvements for achieving the initial proposed goals. Chemical-Vapour-Deposition (CVD) GFET fabrication is considered, which is very promising for large-scale manufacturing (CMOS process compatible), and for that fast-computing large-signal compact modeling for complex circuit design is analysed in depth and optimized, and consequently a set of diverse large-signal static and dynamic GFET circuits are simulated and benchmarked against available measurements assessing the accuracy of the proposed models and deriving scaling prospects. An optimization of the current-to-voltage (I-V) characteristic of a GFET compact model, based upon drift-diffusion carrier transport, is presented. The improved accuracy at the Dirac point extends the model usability for GFETs when scaling parameters such as voltage supply (Vdd), gate length (L), dielectric thickness (tox) and carrier mobility (¿) for large-signal design exploration in circuits. The model accuracy is demonstrated through parameters fitting to measurements taken from CVD GFETs fabricated in the University of Siegen and Technical University of Milan. The script has been written in a standard behavioural language (Verilog-A), and extensively run in a commercial analog circuit simulator (Cadence environment) demonstrating its robustness. Besides a simple capacitance-to-voltage model (C-V), a small-signal parasitic capacitance model fitted to dynamic measurements for self-aligned CVD GFETs available in the literature is added, enabling to forecast maximum-frequency-of-oscillation (fmax) trends for future scaling. A design-oriented characterization of complementary inverter circuits (INV) based on GFETs is presented as well. Our proposed compact model is benchmarked at the circuit level against another compact model based on a virtual-source approach. Furthermore, a benchmark between simulations and measurements of already fabricated CVD GFET INVs is performed, and performance trends when scaling are derived. The same process is repeated for a more complex circuit, namely GFET ring-oscillators (RO). The transient regime simulations yield performance metrics in terms of oscillation frequency (fosc) and dynamic voltage range (¿Vosc), and consequently, against these metrics, a comprehensive design space exploration covering as input design variables parameters as tox, L, and Vdd is carried out. Being aware of the lack of voltage amplification shown by existing GFETs, the design exploration of a cascode amplifier (CAS) targeted to increase voltage gain (Av) by decreasing its output conductance (go) is presented. GFET CAS are simulated to provide design guidelines, they are accordingly fabricated and consequently measured. Performance metrics are provided in terms of go, transconductance (gm) and hence Av. Against these metrics, a quantitative comparison between CAS and GFETs is performed and conclusions are derived. Finally, conclusions on GFETs suitability for future nanoTRX are elaborated. The derived publications come from international collaborations with the Royal Institute of Technology (KTH) in Sweden from 2012 to 2014, and the University of Siegen in Germany from 2014 to 2016.Esta tesis doctoral trata de identificar los requisitos de diseño para nano-ransceptores (nanoTRx) con datos de alta velocidad (de 100 Mbps a 100 Gbps) aplicados a nano-redes inal ámbricas que implican rangos de alcance cortos u ultra-cortos (3 cm - 3 m ); explora FETs de grafeno (GFET), mediante simulaciones y mediciones, como una solución potencial para la implementación de circuitos de alta frecuencia de gran señal, gracias a las extraordinarias propiedades del grafeno como su espesor de un solo átomo y sus portadores de alta movilidad; y finalmente, se discuten los desafíos a los que se enfrentan los GFETs, como la falta de banda prohibida y la alta resistencia de contacto, para lograr proponer alternativas y poder alcanzar los objetivos iniciales propuestos. Las publicaciones derivadas provienen de Colaboraciones internacionales con el KTH en Suecia de 2012 a 2014, y la UniSiegen en Alemania de 2014 a 2016. Se introducen la técnica CVD como un proceso de fabricación de GFETs a gran escala, compatible con tecnología CMOS, muy prometedor; y el modelado compacto de gran señal y computación veloz para el diseño de circuitos complejos es optimizados y analizado en profundidad, Consecuentemente circuitos de gran señal (estáticos y dinámicos) basados en GFET son simulados y comparados con las mediciones disponibles para evaluar la precisi ón de los modelos propuestos y derivar prospecciones de escalado. Se propone una optimización de la característica corriente-voltaje (I-V) de un modelo compacto GFET, basado en el transporte de portadores difusi ón-deriva. La precisión mejorada en el punto de Dirac extiende la usabilidad del modelo para GFETs cuando se dimensionan parámetros para la exploración en diseños de circuitos de gran señal, tales como el voltaje de alimentación (Vdd), la longitud de puerta (L), el espesor diel éctrico (tOX) y la movilidad de portadores (U). La precisión del modelo se demuestra a través de parámetros que se ajustan a mediciones tomadas a partir de CVD GFETs fabricados en la UniSiegen y en el PoliMi. El programa se ha escrito en Verilog-A y se ejecuta extensivamente en un simulador de circuitos anal ógico comercial donde se demuestra su robustez. Además, se lleva a cabo la parametrización de un modelo capacidad-voltaje (C-V) que se ajusta a las mediciones de alta frecuencia de CVD GFETs disponibles en la literatura científica, lo que permite la predicción de la fMAX para el escalado de futuros GFETs. También se presenta una caracterización orientada al diseño de circuitos inversores complementarios (INV) basados en GFETs. Nuestro modelo compacto propuesto se compara a nivel de circuito con otro modelo compacto basado en fuentevirtual. A continuación, se lleva a cabo una comparación a nivel circuito entre las simulaciones y las medidas de INVs ya fabricados basados en CVD GFET, y se obtienen las tendencias de comportamiento al escalarlos. Se repite el mismo proceso para un circuito más complejo, los llamados osciladores-en-anillo GFET (RO). Las simulaciones basadas en transitorios producen métricas de rendimiento en términos de frecuencia de oscilación (fosc) y rango dinámico de voltaje (Vosc), por lo tanto, contra estas métricas, se lleva a cabo una exploración exhaustiva de diseño que abarca Parámetros de variables de diseño como tOX, L y Vdd. Al ser conscientes de la falta de amplificación de voltaje mostrada por los GFETs existentes, se presenta la exploración de diseño de un amplificador cascodo (CAS) diseñado para incrementar la amplificación de voltaje (Av) disminuyendo su conductancia de salida (go). Los GFET CAS son simulados para proporcionar guías de diseño, luego fabricadas y finalmente medidas. Se proporcionan métricas de rendimiento en términos de go, gm, y consecuentemente Av. Frente a estas métricas, se realiza una comparación cuantitativa entre CAS y GFETs y se derivan las conclusiones. Finalmente, se elaboran las conclusiones sobre la idoneidad de los GFET para futuros nanoTR

On the area and energy scalability of wireless network-on-chip: a model-based benchmarked design space exploration

Networks-on-Chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the scalability of NoCs in order to avoid communication to become the next performance bottleneck in multicore processors. Among other alternatives, the concept of Wireless Network-on- Chip (WNoC) has been proposed, wherein on-chip antennas would provide native broadcast capabilities leading to enhanced network performance. Since energy consumption and chip area are the two primary constraints, this work is aimed to explore the area and energy implications of scaling a WNoC in terms of (a) the number of cores within the chip, and (b) the capacity of each link in the network. To this end, an integral design space exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity) and networklevel considerations (number of cores and network architecture). The study is entirely based upon analytical models, which will allow to benchmark the WNoC scalability against a baseline NoC. Eventually, this investigation will provide qualitative and quantitative guidelines for the design of future transceivers for wireless on-chip communication.Peer ReviewedPostprint (author’s final draft

CVD graphene-FET based cascode circuits: a design exploration and fabrication towards intrinsic gain enhancement

This paper presents the design exploration of a basic cascode circuit (CAS) targeted to increase the intrinsic gain A# of a graphene field-effect-transistor (GFET) by decreasing its output conductance go. First, the parameters of a large-signal compact-model, based on drift-diffusion carrier transport, are fit to measurements carried on 2 CVD GFETs, fabricated independently by different research groups. Second, CAS circuits are simulated to perform a design exploration and provide design guidelines. Third, CAS circuits are fabricated and consequently measured. Performance metrics are provided in terms of go, transconductance gm and hence A#. Against these metrics, a quantitative comparison between CAS and GFET is performed and conclusions are derived.Peer ReviewedPostprint (published version

CVD graphene-FET based cascode circuits: a design exploration and fabrication towards intrinsic gain enhancement

This paper presents the design exploration of a basic cascode circuit (CAS) targeted to increase the intrinsic gain A# of a graphene field-effect-transistor (GFET) by decreasing its output conductance go. First, the parameters of a large-signal compact-model, based on drift-diffusion carrier transport, are fit to measurements carried on 2 CVD GFETs, fabricated independently by different research groups. Second, CAS circuits are simulated to perform a design exploration and provide design guidelines. Third, CAS circuits are fabricated and consequently measured. Performance metrics are provided in terms of go, transconductance gm and hence A#. Against these metrics, a quantitative comparison between CAS and GFET is performed and conclusions are derived.Peer Reviewe

Residue conservation in the prediction of protein-protein interfaces

Available from British Library Document Supply Centre- DSC:DXN054307 / BLDSC - British Library Document Supply CentreSIGLEGBUnited Kingdo

3Cat-1: a multi-payload Cubesat-based scientific and technology demonstrator

Peer ReviewedPostprint (published version

3Cat-1: a multi-payload Cubesat-based scientific and technology demonstrator

Peer Reviewe

3Cat-1 project: a multi-payload CubeSat for scientific experiments and technology demonstrators

This article introduces 3 Cat-1, the first project of the Technical University of Catalonia to build and launch a nano-satellite. Its main scope is to develop, construct, assemble, test and launch into a low Earth orbit a CubeSat with seven different payloads (mono-atomic oxygen detector, graphene field-effect transistor, self-powered beacon, Geiger radiation counter, wireless power transfer (WPT), new topology solar cells and WPT experiment), all fitted in a single-unit CubeSat. On one hand, this is mainly an educational project in which the development of some of the subsystems is carried out by undergraduate and postgraduate students. The satellite demonstrates its capabilities as a cost-effective platform to perform small scientific experiments and to demonstrate some of the new technologies that it incorporates

3Cat-1 project: a multi-payload CubeSat for scientific experiments and technology demonstrators

This article introduces 3 Cat-1, the first project of the Technical University of Catalonia to build and launch a nano-satellite. Its main scope is to develop, construct, assemble, test and launch into a low Earth orbit a CubeSat with seven different payloads (mono-atomic oxygen detector, graphene field-effect transistor, self-powered beacon, Geiger radiation counter, wireless power transfer (WPT), new topology solar cells and WPT experiment), all fitted in a single-unit CubeSat. On one hand, this is mainly an educational project in which the development of some of the subsystems is carried out by undergraduate and postgraduate students. The satellite demonstrates its capabilities as a cost-effective platform to perform small scientific experiments and to demonstrate some of the new technologies that it incorporates